Modul CS3110 T

Module part: Computer-Aided Design of Digital Circuits (SchaltEnta)


1 Semester
Turnus of offer:

each winter semester
Credit points:

Course of studies, specific field and terms:
  • Master Entrepreneurship in Digital Technologies 2020 (module part), Module part, Arbitrary semester
  • Master IT-Security 2019 (module part), Module part, 1st or 2nd semester
  • Master Computer Science 2019 (module part), Module part, Arbitrary semester
Classes and lectures:
  • Computer-Aided Design of Digital Circuits (lecture, 2 SWS)
  • Computer-Aided Design of Digital Circuits (exercise, 1 SWS)
  • 20 Hours exam preparation
  • 55 Hours private studies
  • 45 Hours in-classroom work
Contents of teaching:
  • Abstraction levels in circuit design
  • Design cycle and design strategies
  • FPGA architectures
  • Introduction of the hardware description language VHDL
  • Design of standard components in VHDL
  • Circuit design at different abstraction levels
  • Circuit design for synthesis
  • VHDL simulation cycle
  • VHDL circuit design for FPGAs
  • Designing Testbenches
  • High-Level-Synthesis
  • Based on a non-formal description of a digital system, students are able to design digital circuits using VHDL
  • They are able to simulate and test VHDL descriptions
  • They are able to explain the internal structures of FPGAs
  • They are able to determine which VHDL construct will result in which circuit structure
  • They are able to explain the VHDL simulation cycle
  • They are able to write synthesizable VHDL code
Grading through:
  • exam type depends on main module
Responsible for this module:
  • F. Kesel, R. Bartholomä: Entwurf von digitalen Schaltungen und Systemen mit HDLs und FPGAs - Oldenbour Verlag 2009
  • C.Maxfield: The Design Warrior's Guide to FPGAs - Newnes 2004
  • offered only in German

Admission requirements for taking the module:
- None (the competencies of the modules listed under

Letzte Änderung: