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Module guide

Modul CS3110-KP04, CS3110

Computer-Aided Design of Digital Circuits (SchaltEntw)

Duration:


1 Semester
Turnus of offer:


each winter semester
Credit points:


4
Course of studies, specific field and terms:
  • Master Robotics and Autonomous Systems 2019 (optional subject), Additionally recognized elective module, Arbitrary semester
  • Master MES 2020 (optional subject), computer science / electrical engineering, Arbitrary semester
  • Bachelor Computer Science 2016 (optional subject), major subject informatics, Arbitrary semester
  • Bachelor Robotics and Autonomous Systems 2016 (optional subject), computer science, 5th or 6th semester
  • Bachelor IT-Security 2016 (optional subject), computer science, Arbitrary semester
  • Bachelor MES 2014 (optional subject), computer science / electrical engineering, 5th or 6th semester
  • Bachelor Computer Science 2014 (optional subject), central topics of computer science, 5th or 6th semester
  • Bachelor MES 2011 (optional subject), Applied computer science, 3rd, 5th, or 6th semester
  • Bachelor CLS 2010 (optional subject), computer science, 5th or 6th semester
  • Bachelor Computer Science 2012 (optional subject), central topics of computer science, 5th or 6th semester
Classes and lectures:
  • Computer-Aided Design of Digital Circuits (exercise, 1 SWS)
  • Computer-Aided Design of Digital Circuits (lecture, 2 SWS)
Workload:
  • 45 Hours in-classroom work
  • 55 Hours private studies
  • 20 Hours exam preparation
Contents of teaching:
  • Abstraction levels in circuit design
  • Design cycle and design strategies
  • FPGA architectures
  • Introduction of the hardware description language VHDL
  • Design of standard components in VHDL
  • Circuit design at different abstraction levels
  • Circuit design for synthesis
  • VHDL simulation cycle
  • VHDL circuit design for FPGAs
  • Designing Testbenches
  • High-Level-Synthesis
Qualification-goals/Competencies:
  • Based on a non-formal description of a digital system, students are able to design digital circuits using VHDL
  • They are able to simulate and test VHDL descriptions
  • They are able to explain the internal structures of FPGAs
  • They are able to determine which VHDL construct will result in which circuit structure
  • They are able to explain the VHDL simulation cycle
  • They are able to write synthesizable VHDL code
Grading through:
  • written exam
Responsible for this module:
Teachers:
Literature:
  • F. Kesel, R. Bartholomä: Entwurf von digitalen Schaltungen und Systemen mit HDLs und FPGAs - Oldenbour Verlag 2009
  • C.Maxfield: The Design Warrior's Guide to FPGAs - Newnes 2004
Language:
  • English, except in case of only German-speaking participants
Notes:

Admission requirements for taking the module:
- None

Letzte Änderung:
31.7.2024